Edge AI

Start with the MSPM0 G3507: it reads a handwritten digit in 34.4 ms and needs 23 kB of flash and 3.3 kB of RAM. A small neural network that reads a handwritten digit runs as plain C on 9 TI chips; the chart and table show each one.

The projects that run AI on the chip, and what each is good for, are on the AI on the chip page.

Time to read one handwritten digit

One 64-wide convolutional model (99.55% on MNIST, the author's figure), plain C, mean of the stored test digits, fastest chip first. Grey bars are other vendors' chips, for comparison.

Where to start, and the measured numbers

The table gives a starting chip and the numbers behind it: each row is one measured build, time = cycles / clock.

Chipcore, clock, runsTime per digitClock cyclesFlashwhole imageRAMwith the stack

LP-MSPM33C321ACortex-M33, 160 MHz, 3 runs

9.37 ms

1.5M cycles

31.4 kB

14 kB

Raspberry Pi Pico 2 H (Raspberry Pi, comparison)Cortex-M33, 150 MHz, 3 runs

9.61 ms

1.44M cycles

55.8 kB

20.6 kB

LP-EM-CC2755P10Cortex-M33, 96 MHz, 3 runs

11.4 ms

1.09M cycles

40.5 kB

9.6 kB

FRDM-MCXA153 (NXP, comparison)Cortex-M33, 96 MHz, 1 run

13.6 ms

1.3M cycles

40.7 kB

11.6 kB

LP-CC1354P10-1Cortex-M33, 48 MHz, 3 runs

23.5 ms

1.13M cycles

43.6 kB

10.3 kB

LAUNCHXL-F2800137C28x, 120 MHz, 1 run

24.1 ms

2.9M cycles

24 kB

4.1 kB

LP-MSPM0G3507Cortex-M0+, 80 MHz, 10 runs

34.4 ms

2.75M cycles

23 kB

3.3 kB

LP-MSPM0G3519Cortex-M0+, 80 MHz, 10 runs

34.4 ms

2.75M cycles

23.4 kB

3.4 kB

LP-MSPM0G5187Cortex-M0+ with NPU, 80 MHz, 10 runs

34.4 ms

2.75M cycles

not recorded

LP-EM-CC2340R5Cortex-M0+, 48 MHz, 3 runs

57.4 ms

2.76M cycles

39.8 kB

9.4 kB

LP-MSPM0L1306Cortex-M0+, 32 MHz, 10 runs

82.8 ms

2.65M cycles

21.4 kB

3.6 kB

Blank flash or RAM ("not recorded") means no linker map was kept for that build; nothing is estimated.

Try it on a boardA prompt for an AI assistant that builds and runs a small model on the LP-MSPM0G3507, no wiring.

Try small AI models on an LP-MSPM0G3507, no wiring. This prompt builds the room-occupancy networks, not the digit model (digits: handwritten digits). Paste it into an AI assistant that can run commands, or follow the steps. It builds four small room-occupancy networks (636 to 33k weights), runs them on the board and reads back each network's answer and cycle count. The digit model has its own project, handwritten digits.

Run git clone --depth 1 --filter=blob:none --sparse https://github.com/Fox-Red-Labs/fox-red-labs.git, then read fox-red-labs/START.md and follow it to build docs/builds/small-ai-model.md on my LP-MSPM0G3507. Ask me before installing anything or writing to the board.

Five words this page uses

Inference: one run of the model on one input, here one digit or one sensor window.
MAC: a multiply-add, the basic step of a neural network.
int8: weights stored as 8-bit integers instead of floats, so the model is smaller and faster.
NPU: a hardware block that does many MACs at once, beside the CPU.
NNC: TI's Neural Network Compiler, which turns a trained model into C for the CPU or code for the NPU.

The digit model in detailThe stored digit, what the numbers leave out, and every digit model on every chip.

The 99.55% handwritten-digit model reads a digit in 9.37 ms on the MSPM33 C321A (160 MHz) and 82.8 ms on the MSPM0 L1306 (32 MHz): 9 TI chips measured, plus 2 other vendors' chips for comparison. On the TI chips the same model takes 1.09 to 2.90 million clock cycles.

Stored digit 1 of 10, 16 by 16 pixels. The stored label is 3; every chip that recorded the check read it as 3.

Model: BitNetMCU 64-wide convolutional net, 99.55% on the MNIST test set (the author's figure), plain C. Energy per digit was not measured for any chip. Draw-a-digit demo: handwritten digits.

Under 100 ms: 9 of 9 TI chips run the 99.55% model (author's figure, checked here on 10 stored digits); the slowest, the MSPM0 L1306, also uses 90% of its RAM. Least memory: the 1k model, 94.22% on MNIST (the author's figure): 2.79 ms at 32 MHz and a 7.2 kB image with 3.1 kB of RAM (stack included) on the MSPM0 G3507. On the MSPM0 C1104 it fits in 7.2 kB of code and 804 B of RAM, cycles not measured. NPU: no digit-model measurement; the NPU numbers below come from other models. Input, scaling and display work are not in any figure; there are no chip prices or energy figures on this page.

Flash and RAM in this table are read from each build's linker map. Cycles / clock = time: 2.75M cycles at 80 MHz is 34.4 ms. The cycle count rises with the clock because flash needs wait states: the same model takes 2.64M cycles at 32 MHz (1 wait state) and 2.75M at 80 MHz (2 wait states). kB here is 1 kB. Rows with 1 run are single measurements. On-chip accuracy evidence is the 10 stored test digits (10 of 10 right); 99.55% is the model author's MNIST figure.

How to read this table, and what the numbers leave out

Why the same model differs. Time = clock cycles / clock. Cycles depend on the core, the compiler and the flash wait states (extra clock ticks the CPU waits for flash); this page does not isolate which of them causes the spread. Time came from each board's own cycle counter, mean of the 10 stored digits. The digit model's MAC count is not recorded here, so cycles per MAC cannot be given for it.

Reading the picture. 256 pixels go in, 10 scores come out, and the highest score is the answer. Compiler and instruction set differ by row: TI Arm Clang -O3 on the Arm chips, the TI C2000 compiler on the C28x (patched for its 16-bit char), GCC on the comparison chips.

Not measured with the digit model: AM13E230. It has an NPU; no digit-model build or run exists for them, so there is no digit number for the NPU. Flash is the whole image the linker built (model, test program, driver library; the CC13xx and CC23xx images include the SDK, so they are larger than the same model on an MSPM0), RAM as the linker placed it, with the stack the build reserved (the model keeps its working buffers on the stack; deepest use was measured only on the MSPM0G3507, 2,288 of 3 kB, and on the C28x, 1,596 of 2k words, not on the other chips), read from the map files; the C28x figure is quoted from the build notes, in 16-bit words doubled to bytes. "Not recorded" means no linker map was kept for that build; the value is left blank, never estimated. Chip memory is from data/boards.csv. Share of the CPU is inference time divided by one second, with no sensor, scaling or display work. The MSPM0 G3519 was run on its own board (10 runs) and gave the same mean as the G3507, as expected for the same core and clock. Chips are sorted fastest first; comparison rows are from other vendors. Clock cycles compare cores; milliseconds compare what you will buy.

The NPU on a handwriting model

TI's character recognition example reads a 28 by 28 hand-drawn character with a network of 60k parameters (TI's figure). It is not the digit model above, so compare its three builds with each other, not with the digit chips. Measured on the MSPM0 G5187 at 80 MHz, one fixed input, model call only, median of 3 runs. For scale, TI's NNC build on the MSPM33 C321A's Cortex-M33 (no NPU), 160 MHz: 18.1 ms.

Plain C

not measured

No plain C build of TI's handwriting model was timed. The BitNetMCU digit model has no run on this chip either.

TI NNC on the CPU

91.9 ms

7.36 million cycles at 80 MHz. Model only, no test program: flash 66.4 kB (52% of the chip), RAM 8 kB (25%).

NNC on the NPU

10.1 ms

9.1x faster, 0.81 million cycles. Model only, no test program: flash 71.4 kB (56% of the chip), RAM 10.7 kB (34%). NPU runtime code: 298 B. Layers kept on the CPU: not recorded for this example.

Every digit model on every chip, with the row it came from

Chip	Model, MNIST accuracy (the author's)	ms per digit	MHz	Cycles	Flash, whole image	RAM, whole image	Row variant
MSPM33 C321A	1k fully connected, 94.22%	0.22	160	35,785	18.1 kB	14 kB	1k-ticlang-o3-160mhz, 3 runs
Raspberry Pi Pico 2 H	1k fully connected, 94.22%	0.34	150	50,569	45.2 kB	20.6 kB	1k-gcc-o3-150mhz-m33, 3 runs
CC2755P10	1k fully connected, 94.22%	0.37	96	35,594	27.2 kB	9.6 kB	1k-ticlang-o3-96mhz, 3 runs
FRDM-MCXA153	1k fully connected, 94.22%	0.46	96	43,989	30.2 kB	11.6 kB	1k-gcc12-o3-96mhz, 1 runs
CC1354P10-1	1k fully connected, 94.22%	0.93	48	44,766	30.3 kB	10.3 kB	1k-ticlang-o3-48mhz, 3 runs
CC2340R5	1k fully connected, 94.22%	2.09	48	100,161	25.9 kB	9.4 kB	1k-ticlang-o3-48mhz, 3 runs
MSPM0 L1306	1k fully connected, 94.22%	2.52	32	80,485	not recorded	not recorded	1k-ticlang-o3-32mhz, 10 runs
MSPM0 G3507	1k fully connected, 94.22%	2.79	32	89,336	7.2 kB	3.1 kB	1k-ticlang-o3-32mhz, 10 runs
MSPM0 G3519	1k fully connected, 94.22%	2.79	32	89,336	7.2 kB	3.1 kB	1k-ticlang-o3-32mhz, 10 runs
MSPM0 G5187	1k fully connected, 94.22%	2.79	32	89,336	not recorded	not recorded	1k-ticlang-o3-32mhz, 10 runs
FRDM-MCXA153	16-wide CNN, 98.92%	3.46	96	332,079	32.9 kB	11.6 kB	cnn-16small-gcc12-o3-96mhz, 1 runs
MSPM0 L1306	16-wide CNN, 98.92%	20.3	32	650,255	not recorded	not recorded	cnn16-small-ticlang-o3-32mhz, 10 runs
MSPM0 G3507	16-wide CNN, 98.92%	20.6	32	660,687	13.4 kB	3.1 kB	cnn16-small-ticlang-o3-32mhz, 10 runs
MSPM0 G3519	16-wide CNN, 98.92%	20.6	32	660,687	13.4 kB	3.1 kB	cnn16-small-ticlang-o3-32mhz, 10 runs
MSPM0 G5187	16-wide CNN, 98.92%	20.6	32	660,687	not recorded	not recorded	cnn16-small-ticlang-o3-32mhz, 10 runs
FRDM-MCXA153	12k fully connected, 99.02%	2.55	96	244,755	39.8 kB	11.6 kB	12k-gcc12-o3-96mhz, 1 runs
MSPM0 L1306	12k fully connected, 99.02%	12.9	32	412,861	not recorded	not recorded	12k-ticlang-o3-32mhz, 10 runs
MSPM0 G3507	12k fully connected, 99.02%	13.4	32	429,789	19.7 kB	3.1 kB	12k-ticlang-o3-32mhz, 10 runs
MSPM0 G3519	12k fully connected, 99.02%	13.4	32	429,789	19.7 kB	3.1 kB	12k-ticlang-o3-32mhz, 10 runs
MSPM0 G5187	12k fully connected, 99.02%	13.4	32	429,789	not recorded	not recorded	12k-ticlang-o3-32mhz, 10 runs
MSPM33 C321A	64-wide CNN, 99.55%	9.37	160	1,499,307	31.4 kB	14 kB	cnn64-ticlang-o3-160mhz, 3 runs
Raspberry Pi Pico 2 H	64-wide CNN, 99.55%	9.61	150	1,441,038	55.8 kB	20.6 kB	cnn64-gcc-o3-150mhz-m33, 3 runs
CC2755P10	64-wide CNN, 99.55%	11.4	96	1,092,354	40.5 kB	9.6 kB	cnn64-ticlang-o3-96mhz, 3 runs
FRDM-MCXA153	64-wide CNN, 99.55%	13.6	96	1,301,510	40.7 kB	11.6 kB	cnn64-gcc12-o3-96mhz, 1 runs
CC1354P10-1	64-wide CNN, 99.55%	23.5	48	1,125,694	43.6 kB	10.3 kB	cnn64-ticlang-o3-48mhz, 3 runs
LAUNCHXL-F2800137	64-wide CNN, 99.55%	24.1	120	2,897,585	24 kB	4.1 kB	cnn-64-c2000-o4s5-120mhz-flash, 1 runs
MSPM0 G3507	64-wide CNN, 99.55%	34.4	80	2,750,868	23 kB	3.3 kB	cnn64-ticlang-o3-80mhz, 10 runs
MSPM0 G3519	64-wide CNN, 99.55%	34.4	80	2,750,868	23.4 kB	3.4 kB	cnn64-ticlang-o3-80mhz, 10 runs
MSPM0 G5187	64-wide CNN, 99.55%	34.4	80	2,750,868	not recorded	not recorded	cnn64-ticlang-o3-80mhz, 10 runs
CC2340R5	64-wide CNN, 99.55%	57.4	48	2,755,346	39.8 kB	9.4 kB	cnn64-ticlang-o3-48mhz, 3 runs
MSPM0 L1306	64-wide CNN, 99.55%	82.8	32	2,649,196	21.4 kB	3.6 kB	cnn64-ticlang-o3-32mhz, 10 runs

Highest clock measured per chip and model. The 1k model also reads all ten digits on the MSPM0 C1104 (7.2 kB code, 804 B RAM, cycles not measured: no working cycle counter). The Raspberry Pi Pico 2 H also has a Hazard3 RISC-V core: 1.26M cycles per digit, 8.41 ms at 150 MHz, GCC, 3 runs (a different core from the Cortex-M33 row above). Source rows: data/results, test ai_mnist_cycles.

NPU against CPU, same chipWhat the hardware AI engine buys and costs on the same model and clock.

2.3 to 22x

NPU speed-up on the same chip

LP-MSPM0G5187, NPU against CPU, both built with TI's Neural Network Compiler (NNC), by model size.

+12 to +81%

More flash on the NPU than on the CPU

LP-MSPM0G5187, same model.

34 to 61% less

Less RAM on the NPU than on the CPU

LP-MSPM0G5187, same model.

LP-MSPM0G5187

Smallest chip that runs the 8.5k model in under 10 ms

128 kB flash, 32 kB RAM. Fastest build: 2.12 ms on the NPU at 80 MHz.

LP-MSPM0G5187, 80 MHz: time per inferenceRoom-occupancy models, same chip and clock, model call only.

TI NNC on the CPUNNC on the NPU

636 params

4.94 ms

1.29 ms

1.7k params

12 ms

1.45 ms

8.5k params

45.6 ms

2.12 ms

33k params

159 ms

69.4 ms

LP-AM13E230, 200 MHz: time per inferenceRoom-occupancy models, same chip and clock, model call only.

TI NNC on the CPUNNC on the NPU

636 params

0.5 ms

0.11 ms

1.7k params

1.38 ms

0.21 ms

8.5k params

5.54 ms

0.63 ms

33k params

22.9 ms

9.53 ms

The NPU is 2.3 to 22x faster than TI's own NNC build of the same model on the CPU, on the same chip and clock. It uses 34 to 61% less RAM. Against the fastest plain C build it is 1.9 to 17x, but the plain C time also includes input quantization. Times are best case. Flash goes up +12 to +81% on the MSPM0 G5187 and moves between -28 and +39% on the AM13E230.

Chip	Model, params	CPU, ms	NPU, ms	Speed-up	Flash	RAM	Energy above idle
LP-MSPM0G518780 MHz	636	4.94	1.29	3.8x	+81%	−58%	−74%
	1.7k	12	1.45	8.3x	+23%	−55%	−89%
	8.5k	45.6	2.12	21.6x	+12%	−61%	−95%
	33k	159	69.4	2.3x	+58%	−34%	−70%
LP-AM13E230200 MHz	636	0.5	0.11	4.7x	+2%	−58%
	1.7k	1.38	0.21	6.7x	−28%	−55%
	8.5k	5.54	0.63	8.8x	−19%	−61%
	33k	22.9	9.53	2.4x	+39%	−34%

The 33k model gains least (2.3x): NNC left one convolution on the CPU. Its compile log says the layer was not offloaded. A possible cause is that its weights overflow the NPU's accumulator, the 18-bit running total inside each multiply-add; this was not checked. More in the FAQ.

CPU is TI NNC code on the CPU. NPU is the same model on the NPU. Same chip, same clock. Flash, RAM and energy are the change from CPU to NPU. Energy is measured only on the MSPM0 G5187. A layer outside the NPU's limits falls back to the CPU.

More detail: absolute energy, speed against plain C, layers left on the CPU

LP-MSPM0G5187, 80 MHz

Model (MACs: multiply-adds per inference)	NNC on CPU	NPU	Speed-up	vs plain C	Energy above idle, uJ (CPU to NPU)	Whole-board energy, uJ (CPU to NPU)	Flash (CPU to NPU)	RAM (CPU to NPU)	Stayed on CPU
636 params11k MACs	4.94 ms	1.29 ms	3.8x	3.0x	8.73 to 2.31 3.8x less; largest of 3 runs 8.96 to 2.33	276 to 72.1	2.6 kB to 4.7 kB +81%	1.3 kB to 548 B	none
1.7k params34k MACs	12 ms	1.45 ms	8.3x	6.2x	21.3 to 2.36 9.0x less; largest of 3 runs 22.6 to 2.6	673 to 81.2	5.3 kB to 6.5 kB +23%	1.5 kB to 700 B	none
8.5k params158k MACs	45.6 ms	2.12 ms	21.6x	16.7x	85.7 to 4.23 20.3x less; largest of 3 runs 94.3 to 4.92	2,553 to 119	12.6 kB to 14 kB +12%	3.5 kB to 1.4 kB	none
33k params611k MACs	159 ms	69.4 ms	2.3x	1.9x	303 to 92.3 3.3x less; largest of 3 runs 354 to 121	8,928 to 3,856	37.9 kB to 59.8 kB +58%	7 kB to 4.6 kB	1 convolution

Two energy columns, two quantities. Whole-board: the probe's 3.3 V reading for everything on the target side (board circuits and a 16.4 mA floor included) times the model's best-case latency, a steady loop that never sleeps. Above idle: the loop reading minus the same model's idle reading, paired run by run, median of 3 with the largest beside it; a difference of 0.4 to 0.7 mA on 16.4 mA, so it spreads 7 to 32 percent between runs. Neither is an integrated single inference, and neither says anything about a product that sleeps between inferences.

LP-AM13E230, 200 MHz

Model (MACs: multiply-adds per inference)	NNC on CPU	NPU	Speed-up	vs plain C	Energy above idle, uJ (CPU to NPU)	Whole-board energy, uJ (CPU to NPU)	Flash (CPU to NPU)	RAM (CPU to NPU)	Stayed on CPU
636 params11k MACs	0.5 ms	0.11 ms	4.7x	4.6x	not measured	not measured	7 kB to 7.1 kB +2%	1.3 kB to 548 B	none
1.7k params34k MACs	1.38 ms	0.21 ms	6.7x	6.1x	not measured	not measured	12.5 kB to 9 kB -28%	1.5 kB to 700 B	none
8.5k params158k MACs	5.54 ms	0.63 ms	8.8x	8.0x	not measured	not measured	20.5 kB to 16.6 kB -19%	3.5 kB to 1.4 kB	none
33k params611k MACs	22.9 ms	9.53 ms	2.4x	2.0x	not measured	not measured	45.1 kB to 62.5 kB +39%	7 kB to 4.6 kB	1 convolution

AccuracyHow accurate small models are, and why more parameters did not buy more.

More parameters did not buy accuracy. Int8 accuracy on 4 classes is 88.4 to 90.9% from 636 to 8.5k parameters, then falls to 85.4% at 33k while time on the MSPM0 G3507 grows 3.7x. The cause of the drop is not tested.

Port check: the same answers as the Mac

On every board, the 20 stored test vectors give the same class as onnxruntime, the Mac's model runtime, in NPU and CPU builds alike. This checks the port and says nothing about accuracy.

Accuracy on data the model did not train on

The figures above are int8 accuracy on 1,001 held-out windows, measured on the Mac. Int8 is the 8-bit integer form that runs on the chip.
Those windows were cut in 48-minute blocks from the same room and the same days as the training data, so near-duplicate conditions sit on both sides.
A stricter test holds out whole days: an 8k model trained once on the December days and scored on 1,983 January windows it never saw. Accuracy is 87.7%, but balanced accuracy is 40.2%. It called 159 of 170 three-person windows empty.
Read the same-day figure above as the optimistic one, and this day figure as what a new day in the same room gives.
Balanced accuracy is the average of how often each class is caught, so a model that calls everything empty scores low on it.
Why the drop: LP-MSPM0G5187 FAQ.

Live sensors

No board has run it on live sensors, and not all 1,001 windows on a board.

This is a judgment. It was not measured. 80 to 95% is fine when a wrong answer costs a minute, like a light or a screen. Near 100% is needed when a miss costs something, like a fault or fall alarm. Then watch the class you cannot afford to miss instead of overall accuracy.

The accuracy table, the digit models, and time against size

Model, params	4 classes, float, %	4 classes, int8, %	Empty vs occupied, int8, %	Balanced, int8, %
636	89.1	88.4	100.0	69.1
1.7k	89.1	88.5	99.8	65.0
8.5k	92.4	90.9	100.0	74.7
33k	87.4	85.4	98.6	60.5

Test set: 770 empty windows, 65 with one person, 65 with two, 101 with three. Float is the model before int8 quantization; "empty vs occupied" counts a miss only when an empty room is called occupied or the reverse; "balanced" averages the recall of the four classes. The plain C code matches the quantized model on all 1,001 windows on the Mac.

Diminishing return: the 636-parameter model already separates an empty room from an occupied one (100%); after that, parameters cost time and flash without adding accuracy.

Digit reading shows the same shape: the 1k model reads 94.2% of the MNIST test set. The 12k fully connected model reads 99.0% for 4.8x the cycles. The 64-wide CNN reads 99.6% for 29.6x the cycles of the 1k model. Cycles are measured here, on the MSPM0 G3507 at 32 MHz. The accuracies are the author's, on MNIST's held-out set. The 10 of 10 is a port check, not an accuracy. Digits drawn on the touch screen were read but not counted.

Fit: chip by model sizeEvery chip with a row runs all four models except three: the LP-MSPM0C1104 holds none of them, the LP-MSPM0L1306 cannot hold the 33k model, and the LAUNCHXL-F28P65X has no result for the 33k model (its RAM build does not fit). The first two run out of RAM first.

Chip	636 params	1.7k params	8.5k params	33k params
LP-MSPM0C1104Cortex-M0+, 16 kB flash, 1 kB RAM	does not fit: RAM	does not fit: RAM	does not fit: RAM	does not fit: RAM
LP-MSPM0L1306Cortex-M0+, 64 kB flash, 4 kB RAM	9.3 msPlain C, 6.3 kB / 1.1 kB	21.9 msPlain C, 9.5 kB / 1.1 kB	83.7 msPlain C, 16.6 kB / 2.1 kB	does not fit: RAM
LP-EM-CC2340R5Cortex-M0+, 512 kB flash, 36 kB RAM	7.03 msPlain C, 6.3 kB / 1.1 kB	16.6 msPlain C, 9.5 kB / 1.1 kB	63.2 msPlain C, 16.6 kB / 2.1 kB	229 msPlain C, 40.7 kB / 4.1 kB
NUCLEO-U083RCCortex-M0+, 256 kB flash, 40 kB RAM	8.05 msPlain C (GCC), not recorded	15.3 msPlain C (GCC), not recorded	52 msPlain C (GCC), not recorded	186 msPlain C (GCC), not recorded
LP-MSPM0G3507Cortex-M0+, 128 kB flash, 32 kB RAM	4 msPlain C, 6.3 kB / 1.1 kB	9.05 msPlain C, 9.5 kB / 1.1 kB	35.3 msPlain C, 16.6 kB / 2.1 kB	129 msPlain C, 40.7 kB / 4.1 kB
LP-MSPM0G3519Cortex-M0+, 512 kB flash, 128 kB RAM	3.91 msPlain C, 6.3 kB / 1.1 kB	9.04 msPlain C, 9.5 kB / 1.1 kB	35.3 msPlain C, 16.6 kB / 2.1 kB	129 msPlain C, 40.7 kB / 4.1 kB
LP-MSPM0G5187Cortex-M0+ with NPU, 128 kB flash, 32 kB RAM	1.29 msNPU, 4.7 kB / 548 B	1.45 msNPU, 6.5 kB / 700 B	2.12 msNPU, 14 kB / 1.4 kB	69.4 msNPU, 59.8 kB / 4.6 kB
LP-CC1354P10-1Cortex-M33, 1 MB flash, 296 kB RAM	2.13 msNNC CPU, 6.5 kB / 1.3 kB	6.05 msNNC CPU, 12 kB / 1.5 kB	24.4 msNNC CPU, 19.2 kB / 3.5 kB	91 msNNC CPU, 43.7 kB / 7 kB
LP-EM-CC2755P10Cortex-M33, 1 MB flash, 162 kB RAM	0.95 msNNC CPU, 6.5 kB / 1.3 kB	2.6 msPlain C, 10.1 kB / 1.1 kB	10.5 msPlain C, 16.6 kB / 2.1 kB	39 msPlain C, 40.8 kB / 4.1 kB
CC35X1Cortex-M33, 8 MB flash, 1.1 MB RAM	0.6 msPlain C, not recorded	1.54 msPlain C, not recorded	6.25 msPlain C, not recorded	24.4 msPlain C, not recorded
LP-MSPM33C321ACortex-M33, 1 MB flash, 256 kB RAM	0.75 msPlain C, not recorded	1.86 msPlain C, not recorded	7.38 msPlain C, not recorded	27.2 msPlain C, not recorded
LP-AM13E230Cortex-M33 with TMU and NPU, 512 kB flash, 128 kB RAM	0.11 msNPU, 7.1 kB / 548 B	0.21 msNPU, 9 kB / 700 B	0.63 msNPU, 16.6 kB / 1.4 kB	9.53 msNPU, 62.5 kB / 4.6 kB
LAUNCHXL-F2800137C28x, 256 kB flash, 36 kB RAM	1.12 msNNC CPU, 5 kB / 1.8 kB	2.6 msNNC CPU, 10.4 kB / 3.1 kB	9.05 msNNC CPU, 24.6 kB / 6.1 kB	30.8 msNNC CPU, 73.4 kB / 12.2 kB
LAUNCHXL-F28P65XC28x, 1.2 MB flash, 248 kB RAM	0.89 msPlain C, 4.2 kB in RAM	2.37 msPlain C, 6.6 kB in RAM	8.38 msPlain C, 21.1 kB in RAM	no row; the RAM build does not fit

Each cell: time of the fastest build measured, which build, then flash / RAM for the model alone (weights, model code, NPU runtime; not the test program, driver library or stack). "not recorded" means no linker map was kept for that build. On the C28x a byte is 16 bits, so its weights take about twice the room. A build with code in RAM shows its whole size as RAM.

Every chip side by sideAcross chips the CPU builds take 6.3 to 19.2 cycles per MAC and the NPU builds 0.8 to 1.1.

Chip	Core, clock	CPU cycles per MAC	NPU cycles per MAC	Best time	Energy, CPU / NPU	Flash / RAM, best build
LP-AM13E230	M33 with TMU and NPU, 200 MHz	6.4Plain C	0.8	0.63 msNPU	not measured	16.6 kB / 1.4 kB
LP-MSPM0G5187	M0+ with NPU, 80 MHz	17.9Plain C	1.1	2.12 msNPU	85.7 / 4.23 uJ	14 kB / 1.4 kB
CC35X1	M33, 160 MHz	6.3Plain C	no NPU	6.25 msPlain C	not measured	not recorded
LP-MSPM33C321A	M33, 160 MHz	7.5Plain C	no NPU	7.38 msPlain C	not measured	not recorded
LAUNCHXL-F28P65X	C28x, 200 MHz	10.6Plain C	no NPU	8.38 msPlain C	not measured	21.1 kB in RAM
LAUNCHXL-F2800137	C28x, 120 MHz	6.9NNC CPU	no NPU	9.05 msNNC CPU	not measured	24.6 kB / 6.1 kB
LP-EM-CC2755P10	M33, 96 MHz	6.4Plain C	no NPU	10.5 msPlain C	not measured	16.6 kB / 2.1 kB
LP-CC1354P10-1	M33, 48 MHz	7.4NNC CPU	no NPU	24.4 msNNC CPU	not measured	19.2 kB / 3.5 kB
LP-MSPM0G3507	M0+, 80 MHz	17.9Plain C	no NPU	35.3 msPlain C	not measured	16.6 kB / 2.1 kB
LP-MSPM0G3519	M0+, 80 MHz	17.9Plain C	no NPU	35.3 msPlain C	not measured	16.6 kB / 2.1 kB
NUCLEO-U083RC	M0+, 56 MHz	15.8Plain C	no NPU	52 msPlain C	not measured	not recorded
LP-EM-CC2340R5	M0+, 48 MHz	19.2Plain C	no NPU	63.2 msPlain C	not measured	16.6 kB / 2.1 kB
LP-MSPM0L1306	M0+, 32 MHz	17.0Plain C	no NPU	83.7 msPlain C	not measured	16.6 kB / 2.1 kB

Sorted by best time. 8.5k-parameter model, int8. Cycles per MAC = cycles per inference divided by 158k MACs. Each row uses the best plain C or NNC build measured on that chip, so compilers differ (see "How it was measured"); energy is only measured on the MSPM0 G5187, EnergyTrace, net of idle.

TI's other example models (G5187)Beyond occupancy, 9 TI example models have timings on a board and 0 are built but not run. On the LP-MSPM0G5187 the NPU is 3.8 to 83 times faster on the examples that ran.

Model type

Waveform hello world. Classifies a synthetic waveform (a first-run check). 14k parameters (TI). TI publishes no accuracy for it.

NPU is 9.7x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G3507: 125 ms at 32 MHz, 1 run, model call only MSPM0 G3519: 126 ms at 32 MHz, 3 runs MSPM0 G5187: 126 ms at 32 MHz, 3 runs	not published	not published	24.4 kB / 3.4 kB
NPU	MSPM0 G5187: 13 ms at 32 MHz, 3 runs, model call only	not published	not published	24.6 kB / 3.7 kB

Waveform classifier. Classifies multichannel waveforms. 14k parameters (TI). TI reports an R square of 100% on its own data. That figure is TI's.

NPU is 9.3x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G5187: 54.3 ms at 80 MHz, 3 runs MSPM33 C321A: 12.4 ms at 160 MHz, 1 run, model call only	54.1 ms	21.7 kB / 3.1 kB	109 kB / 9.9 kB
NPU	MSPM0 G5187: 5.86 ms at 80 MHz, 3 runs	5.84 ms	21.5 kB / 3.3 kB	109.3 kB / 10.2 kB

Gearbox fault. Finds a worn gearbox from vibration. 1.4k (2.7k for the NPU version) parameters (TI). TI reports ~99.9% accuracy on its own data. That figure is TI's.

NPU is 3.8x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G5187: 37.1 ms at 32 MHz, 3 runs, model call only	not published	10.1 kB / 1.9 kB	11.3 kB / 3 kB
NPU	MSPM0 G5187: 9.65 ms at 32 MHz, 3 runs, model call only	not published	8.9 kB / 2.2 kB	13.5 kB / 2.2 kB

Motor bearing anomaly. Tells a normal bearing from an abnormal one. 327 parameters (TI). TI reports 100% accuracy on its own data. That figure is TI's.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G3507: 13.1 ms at 80 MHz, 1 run, feature extraction plus model	21.4 ms	3.2 kB / 2.3 kB	not published
NPU	no row	not published	not published	not published

Motor bearing fault. Names one of 6 bearing conditions from vibration. 3.6k parameters (TI). TI reports ~99% accuracy on its own data. That figure is TI's.

NPU is 83.2x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G3507: 176 ms at 80 MHz, 1 run, feature extraction plus model MSPM0 G5187: 107 ms at 80 MHz, 3 runs, model call only	229 ms	6.4 kB / 16.6 kB	117 kB / 20.1 kB
NPU	MSPM0 G5187: 1.28 ms at 80 MHz, 3 runs, model call only	1,088 ms	5.1 kB / 12.7 kB	116.2 kB / 16.1 kB

TI's times are for the whole pipeline with feature extraction; the measured times are the model call only.

Fan blade fault. Spots a damaged fan blade from vibration. 5.2k parameters (TI). TI reports ~99% accuracy on its own data. That figure is TI's.

NPU is 9.7x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G5187: 1.76 ms at 80 MHz, 3 runs, model call only	2.09 ms	1.4 kB / 1 kB	89.2 kB / 17.1 kB
NPU	MSPM0 G5187: 0.18 ms at 80 MHz, 3 runs, model call only	0.16 ms	2.2 kB / 901 B	90.3 kB / 16.9 kB

Fall detection. Tells a fall from normal movement, from an accelerometer. 6k parameters (TI). TI reports 97.65% accuracy on its own data. That figure is TI's.

NPU is 6.0x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G5187: 8.57 ms at 80 MHz, 3 runs, model call only	8.56 ms	13 kB / 983 B	103.1 kB / 6.7 kB
NPU	MSPM0 G5187: 1.44 ms at 80 MHz, 3 runs, model call only	0.67 ms	14 kB / 717 B	104.6 kB / 6.5 kB

ECG anomaly. Flags an unusual heartbeat trace (autoencoder). 55k parameters (TI). TI reports ~97% accuracy on its own data. That figure is TI's.

NPU is 5.1x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G5187: 497 ms at 80 MHz, 3 runs, model call only	not published	64.8 kB / 18.4 kB	71.3 kB / 26.7 kB
NPU	MSPM0 G5187: 96.6 ms at 80 MHz, 3 runs, model call only	not published	88 kB / 13.2 kB	95.7 kB / 21.5 kB

Character recognition. Reads a hand-drawn character from an image. 60k parameters (TI). TI reports ~99% accuracy on its own data. That figure is TI's.

NPU is 9.1x faster than the CPU build on the same chip. Rows at the same clock.

Build	Measured	TI published time	TI flash / RAM	Image, flash / RAM
CPU	MSPM0 G5187: 91.9 ms at 80 MHz, 3 runs, model call only MSPM33 C321A: 18.1 ms at 160 MHz, 1 run, model call only	89.8 ms	68 kB / 8.1 kB	72.2 kB / 11.7 kB
NPU	MSPM0 G5187: 10.1 ms at 80 MHz, 3 runs, model call only	6.05 ms	73 kB / 10.9 kB	79 kB / 14.5 kB

TI C2000Ware examples as shipped, one run each at 120 MHz. TI gives no parameter table for these.

Example	Time	Conditions
generic timeseries regression	0.22 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
forecasting pmsm rotor temp	0.62 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
hvac indoor temp forecast	1.04 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
torque measurement	5.6 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
blower imbalance	6.25 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
motor fault	6.26 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
generic timeseries forecasting	8.09 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
fan blade anomalydetection	23.6 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
washing machine load weighing	24.9 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash
generic timeseries anomalydetection	37.6 ms	TI build: application --opt_level=off, NNC mod.a on CPU, code in flash

Wake word: on the MSPM0 G5187 the unchanged model detected a synthetic "OK Kilby" in 20 of 20 tries for each of six voices (replayed audio, not the board's own microphone). Not run means the example waits for sensor data or a PC tool.

Every TI AI example, by board

TI example

LAUNCHXL-F2800137C28x, 120 MHz, FPU

LP-MSPM0G3507M0+, 80 MHz, no FPU

LP-AM13E230M33, 200 MHz, FPU

LP-MSPM33C321AM33, 160 MHz, FPU

LP-MSPM0G5187M0+, 80 MHz, no FPU

Motor bearing fault

LAUNCHXL-F2800137Works6.26 ms at 120 MHz; model only, 751k cycles; feature extraction adds 103k cycles (0.86 ms). TI's build as shipped: application at --opt_level=off, model from NNC. Example motor_fault, 1 run.

LP-MSPM0G3507Works176 ms at 80 MHz; feature extraction plus model; all 6 classes correct. MSPM0's own version of this demo, not the same model. TI publishes 229.01 ms; the difference is not investigated. Example motor_bearing_fault_detection_ai, 1 run.

LP-AM13E230Works0.41 ms at 200 MHz; 82k cycles for one model run. Example motor_fault, 1 run.

LP-MSPM33C321AWorks23.4 ms at 32 MHz; model call only; 750k cycles for one model run. Run at the example's own 32 MHz setting, not the board's 160 MHz. Example motor_fault, 1 run.

LP-MSPM0G5187Works107 ms at 80 MHz; model call only. On the NPU: 1.28 ms, 83 times faster. TI's README publishes 229.01 ms for the whole pipeline. Example motor_bearing_fault_detection_ai, 1 run.

Fan blade anomaly

LAUNCHXL-F2800137Works23.6 ms at 120 MHz; model only, 2.83M cycles; feature extraction adds 102k cycles (0.85 ms). TI's build as shipped: application at --opt_level=off, model from NNC. Example fan_blade_anomalydetection, 1 run.

LP-MSPM0G3507Not for this chipNo version in the MSPM0 SDK

LP-AM13E230Works5.43 ms at 200 MHz; 1.09M cycles for one model run. Example fan_blade_anomalydetection, 1 run.

LP-MSPM33C321ANot for this chipNo version in the MSPM33 SDK

LP-MSPM0G5187Not for this chipNo version in the MSPM0 SDK

Blower imbalance

LAUNCHXL-F2800137Works6.25 ms at 120 MHz; model only, 750k cycles; feature extraction adds 103k cycles (0.86 ms). TI's build as shipped: application at --opt_level=off, model from NNC. Example blower_imbalance, 1 run.

LP-MSPM0G3507Not for this chipNearest is motor_fan_blade_fault_ai, which needs an ADXL355 accelerometer

LP-AM13E230Not for this chipNo version found in the AM13E2x SDK

LP-MSPM33C321AWorks23 ms at 32 MHz; model call only; 736k cycles for one model run. Run at the example's own 32 MHz setting, not the board's 160 MHz. Example blower_imbalance, 1 run.

LP-MSPM0G5187Not for this chipNearest is motor_fan_blade_fault_ai, which needs an ADXL355 accelerometer

Torque estimate

LAUNCHXL-F2800137Works5.6 ms at 120 MHz; model only, 672k cycles; feature extraction adds 8k cycles (0.07 ms). TI's build as shipped: application at --opt_level=off, model from NNC. Example torque_measurement, 1 run.

LP-MSPM0G3507Not for this chipNo version in the MSPM0 SDK

LP-AM13E230Not for this chipNo version found in the AM13E2x SDK

LP-MSPM33C321AWorks16.7 ms at 32 MHz; model call only; 534k cycles for one model run. Run at the example's own 32 MHz setting, not the board's 160 MHz. Example torque_measurement, 1 run.

LP-MSPM0G5187Not for this chipNo version in the MSPM0 SDK

Time-series anomaly

LAUNCHXL-F2800137Works37.6 ms at 120 MHz; model only, 4.52M cycles; feature extraction adds 18k cycles (0.15 ms). TI's build as shipped: application at --opt_level=off, model from NNC. Example generic_timeseries_anomalydetection, 1 run.

LP-MSPM0G3507Not for this chipNo version in the MSPM0 SDK

LP-AM13E230Not for this chipNo version found in the AM13E2x SDK

LP-MSPM33C321AWorks67.1 ms at 32 MHz; model call only; 2.15M cycles for one model run. Run at the example's own 32 MHz setting, not the board's 160 MHz. Example generic_timeseries_anomalydetection, 1 run.

LP-MSPM0G5187Not for this chipNo version in the MSPM0 SDK

Waveform classifier

LAUNCHXL-F2800137

LP-MSPM0G3507Works125 ms at 32 MHz; model call only; TI prebuilt model. MSPM0's own version of this demo, not the same model. Run at the example's own 32 MHz setting, not the board's 80 MHz. Example hello_world_ai, 1 run.

LP-AM13E230Not for this chipNo version found in the AM13E2x SDK

LP-MSPM33C321AWorks41.5 ms at 32 MHz; model call only; 1.33M cycles for one model run. Run at the example's own 32 MHz setting, not the board's 160 MHz. Example generic_timeseries_classification, 1 run.

LP-MSPM0G5187Works126 ms at 32 MHz; model call only. On the NPU: 13 ms, 9.7 times faster. Run at the example's own 32 MHz setting, not the board's 80 MHz. Example hello_world_ai, 1 run.

Waveform classifier on the ADC

LAUNCHXL-F2800137

LP-MSPM0G3507

LP-AM13E230

LP-MSPM33C321A

LP-MSPM0G5187Works54.3 ms at 80 MHz; model call only. On the NPU: 5.86 ms, 9.3 times faster. Example waveform_classifier_ai, 1 run.

Gearbox fault

LAUNCHXL-F2800137

LP-MSPM0G3507

LP-AM13E230

LP-MSPM33C321A

LP-MSPM0G5187Works37.1 ms at 32 MHz; model call only. On the NPU: 9.65 ms, 3.8 times faster. Run at the example's own 32 MHz setting, not the board's 80 MHz. Example gearbox_fault_diagnosis_ai, 1 run.

PIR presence

LAUNCHXL-F2800137Not for this chipNo version in C2000Ware

LP-MSPM0G3507

LP-AM13E230Not for this chipNo version found in the AM13E2x SDK

LP-MSPM33C321AWorks65.3 ms at 32 MHz; model call only; 2.09M cycles for one model run. Run at the example's own 32 MHz setting, not the board's 160 MHz. Example pir_detection_ai, 1 run.

LP-MSPM0G5187

Works timed on the board; TI's stored test vectors give the expected answersNot for this chip TI ships no version of it for that chip

Which SDK ships what: the showcase list.

What each part can and cannot runMemory decides before speed does on the small chips.

LP-MSPM0C1104 (16 kB flash, 1 kB RAM, CPU only): none of the four models fits (RAM). The BitNetMCU 1k digit model does fit: 10 ms per digit at 24 MHz.
LP-MSPM0L1306 (64 kB flash, 4 kB RAM, CPU only): ran up to 8.5k parameters; the 33k model does not fit: RAM.
LP-EM-CC2340R5 (512 kB flash, 36 kB RAM, CPU only): ran up to 33k parameters; RAM runs out first, at about 287k parameters (flash at 444k).
NUCLEO-U083RC (256 kB flash, 40 kB RAM, CPU only): ran up to 33k parameters; flash and RAM were not recorded for it.
LP-MSPM0G3507 (128 kB flash, 32 kB RAM, CPU only): ran up to 33k parameters; flash runs out first, at about 111k parameters in the NNC CPU build (RAM at 255k).
LP-MSPM0G3519 (512 kB flash, 128 kB RAM, CPU only): ran up to 33k parameters; flash runs out first, at about 444k parameters in the NNC CPU build (RAM at 1.02M).
LP-MSPM0G5187 (128 kB flash, 32 kB RAM, has an NPU): ran up to 33k parameters; flash runs out first, at about 111k parameters in the NNC CPU build (RAM at 255k).
LP-CC1354P10-1 (1 MB flash, 296 kB RAM, CPU only): ran up to 33k parameters; flash runs out first, at about 825k parameters in the Plain C build (RAM at 2.36M).
LP-EM-CC2755P10 (1 MB flash, 162 kB RAM, CPU only): ran up to 33k parameters; flash runs out first, at about 825k parameters in the Plain C build (RAM at 1.29M).
LP-EM-CC35X1 (8 MB flash, 1.1 MB RAM, CPU only): ran up to 33k parameters; flash and RAM were not recorded for it.
LP-MSPM33C321A (1 MB flash, 256 kB RAM, CPU only): ran up to 33k parameters; flash and RAM were not recorded for it.
LP-AM13E230 (512 kB flash, 128 kB RAM, has an NPU): ran up to 33k parameters; flash runs out first, at about 412k parameters in the Plain C build (RAM at 1.02M).
LAUNCHXL-F2800137 (256 kB flash, 36 kB RAM, CPU only): ran up to 33k parameters; flash runs out first, at about 125k parameters in the Plain C build (RAM at 278k).
LAUNCHXL-F28P65X (1.2 MB flash, 248 kB RAM, CPU only): ran up to 8.5k parameters, from RAM; the 33k model's RAM build does not fit and no other build was run.

The ceilings use the smallest bytes per parameter among the builds on that chip, at the largest model that ran, and ignore your own program, so treat them as upper bounds to check against a real build. The ceiling is a straight-line guess from the four models.

How it was measured and the toolchainIntel Mac, 20 test vectors, best of 5; compilers differ by chip; NNC runs on Linux in GitHub Actions.

Four room-occupancy models (636 to 33k parameters, int8, from the model sweep) were built for every board where each linked. Every build that ran gave the same answers as the Mac on 20 test windows. Time is the fastest of 20 vectors, best of 5 per vector; NNC builds are medians of 3 runs, each after a fresh flash. The plain C timing also includes input quantization, so the NPU-against-plain-C gain is not like for like. Times are best case and cover the model call only: 3 runs agreed to the cycle, and the slowest of the 20 vectors ran up to 3.3% longer on the MSPM0 G5187 (the slowest-vector column of its results file). The NPU needs channel counts in multiples of 4, pooling kernels up to 4 and fully connected inputs of at least 16; a layer outside those limits falls back to the CPU. Measured 2026-10-05 to 2026-11-02 on an Intel Mac. Cycles = ms x clock. Flash and RAM come from each build's linker map: weights, model code and any NPU runtime, without the test program, driver library, C library, stack or the 20 test vectors. Compilers differ by chip (TI Arm Clang 4.0.4 or 5.1.1, the C2000 compiler 25.11.1, GCC on the NUCLEO); the build under each line is named in the chart tips and the table. Energy is EnergyTrace on the onboard probe, loop current minus idle current, 3 captures. 1 kB = 1,024 bytes.

A model goes from training to chip like this: train with TI Tensorlab (or PyTorch) with quantization-aware training, export to ONNX, then TI's Neural Network Compiler (NNC) turns it into C for the CPU or into NPU code, packaged as a library (mod.a) you link into a CCStudio project. NNC has no Intel Mac build, so it runs in a GitHub Actions job on Linux and download the library. That is why the NPU numbers here come from a fixed set of four models and not from any model you type in. Tensorlab 1.4 pins torch 2.11, which also keeps training off this Mac. TI lists hardware NPUs on more chips than are tested here (its device matrix includes the F28P55 and MSPM33C34, and its documents disagree about the F28P65). This page covers the two NPU chips that ran: the MSPM0 G5187 and the AM13E230. The LAUNCHXL-F28P65X rows are CPU only.

Cycles per MAC, every board

Cycles per multiply-accumulate, four room-occupancy modelsLower is better. Fastest build of each model on each board, any build (plain C or TI NNC code on the CPU, or TI NNC code on an NPU, marked in the table). Cycles per MAC is the number that carries over to your model. It still rises with the clock, probably from flash wait states. The same build, more cycles: LP-MSPM0G5187: 8 to 14% more at 80 MHz than at 32 MHz; LP-MSPM33C321A: 17 to 23% more at 160 MHz than at 32 MHz. No bar: 33k parameters on the LP-MSPM0L1306 does not fit (RAM).

636 parameters1.7k parameters8.5k parameters33k parameters

LP-MSPM0C1104M0+, 24 MHz, no FPU

does not fit: RAM, all four models (link only)

LP-MSPM0L1306M0+, 32 MHz, no FPU

26.3

20.7

LP-MSPM0G3507M0+, 80 MHz, no FPU

28.2

21.4

17.9

LP-EM-CC2340R5M0+, 48 MHz, no FPU

29.8

23.5

19.2

LP-CC1354P10-1M33, 48 MHz, FPU

8.6

7.4

7.2

LAUNCHXL-F2800137C28x, 120 MHz, FPU

11.8

9.2

6.9

LP-AM13E230M33, 200 MHz, FPU

1.9

1.2

0.8

3.1

LP-EM-CC2755P10M33, 96 MHz, FPU

8.1

7.4

6.4

6.1

LP-EM-CC35X1M33, 160 MHz, FPU

8.5

7.3

6.3

6.4

ESP32-C6-DevKitC-1-N8RISC-V, 160 MHz, no FPU

15.8

10.2

7.2

7.1

LAUNCHXL-F28P65XC28x, 200 MHz, FPU

15.8

10.6

15.7

FRDM-MCXA153Cortex-M33, 96 MHz, no FPU

14.1

7.6

7.2

LP-MSPM0G3519M0+, 80 MHz, no FPU

27.6

21.4

17.9

LP-MSPM0G5187M0+, 80 MHz, no FPU

9.1

3.4

1.1

9.1

LP-MSPM33C321AM33, 160 MHz, FPU

10.6

8.8

7.5

7.1

NUCLEO-U083RCM0+, 56 MHz, no FPU

34.1

21.6

15.7

14.6

Raspberry Pi Pico 2 HCortex-M33, 150 MHz, no FPU

9.9

8.4

6.5

6.4

SK-TDA4VM2x Cortex-A72 + C7x/MMA + 2x C66x + 6x R5F, 2000 MHz, no FPU

3.1

2.6

2.4

2.2

Every build: time, cycles and cycles per MAC per model

Board	Core, clock, FPU	Accelerator used	Compiler and build	636 parameters	1.7k parameters	8.5k parameters	33k parameters
MSPM0 C1104	M0+, 24 MHz, no FPU	none	TI Arm Clang 5.1.1 plain C, -O3 `c-o3`	Not for this chipbuffers 1.2 kB (model 1.1 kB plus 48 B for the test program): RAM short by 688 B beside the stack; .text 7.3 kB also over the free flash	Not for this chipbuffers 1.2 kB (model 1.1 kB plus 48 B for the test program): RAM short by 688 B beside the stack; .text 9.3 kB also over the free flash	Not for this chipbuffers 2.2 kB: RAM short by 1.7 kB beside the stack; .rodata 18.8 kB (weights 9.1 kB plus test vectors) over the 16 kB of flash	Not for this chipbuffers 4.2 kB: RAM short by 3.7 kB beside the stack; weights alone 33.6 kB are over the 16 kB of flash
MSPM0 C1104	M0+, 24 MHz, no FPU	none	TI Arm Clang 5.1.1 plain C, -Os `c-os`	Not for this chipbuffers 1.2 kB (model 1.1 kB plus 48 B for the test program): RAM short by 688 B beside the stack	Not for this chipbuffers 1.2 kB (model 1.1 kB plus 48 B for the test program): RAM short by 688 B beside the stack	Not for this chipbuffers 2.2 kB: RAM short by 1.7 kB beside the stack; .rodata 19.2 kB (weights 9.1 kB plus test vectors) over the 16 kB of flash	Not for this chipbuffers 4.2 kB: RAM short by 3.7 kB beside the stack; weights alone 33.6 kB are over the 16 kB of flash
MSPM0 L1306	M0+, 32 MHz, no FPU	none	TI Arm Clang 4.0.4 prebuilt model library (built for the G3507), test program 5.1.1 plain C, -O3 `c-o3`	9.3 ms298k cycles26.3 per MAC	21.9 ms701k cycles20.7 per MAC	83.7 ms2.68M cycles17.0 per MAC	Not for this chipbuffers alone exceed 4 kB RAM; linker error
MSPM0 L1306	M0+, 32 MHz, no FPU	none	TI Arm Clang 4.0.4 prebuilt model library (built for the G3507), test program 5.1.1 plain C, -Os `c-os`	12 ms384k cycles33.9 per MAC	28.3 ms906k cycles26.7 per MAC	99.9 ms3.2M cycles20.3 per MAC	Not for this chipbuffers alone exceed 4 kB RAM; linker error
MSPM0 G3507	M0+, 80 MHz, no FPU	none (the chip has MATHACL; integer model code does not use it)	TI Arm Clang 4.0.4 prebuilt model library (built for the G3507), test program 5.1.1 plain C, -O3 `c-o3`	4 ms320k cycles28.2 per MAC	9.05 ms724k cycles21.4 per MAC	35.3 ms2.82M cycles17.9 per MAC	129 ms10.4M cycles17.0 per MAC
MSPM0 G3507	M0+, 80 MHz, no FPU	none (the chip has MATHACL; integer model code does not use it)	TI Arm Clang 4.0.4 prebuilt model library (built for the G3507), test program 5.1.1 plain C, -Os `c-os`	4.68 ms374k cycles33.1 per MAC	10.9 ms870k cycles25.7 per MAC	39.9 ms3.2M cycles20.2 per MAC	199 ms16M cycles26.1 per MAC
MSPM0 G3507	M0+, 80 MHz, no FPU	none (the chip has MATHACL; integer model code does not use it)	TI NNC 2.1.2 with TI Arm Clang 5.1.1 TI NNC code, -Os `nnc-cpu`	4.95 ms396k cycles35.0 per MAC	12 ms958k cycles28.3 per MAC	45.6 ms3.65M cycles23.1 per MAC	159 ms12.7M cycles20.9 per MAC
CC2340R5	M0+, 48 MHz, no FPU	none	TI Arm Clang 4.0.4 prebuilt model library (built for the G3507), test program 5.1.1 plain C, -O3 `c-o3`	7.03 ms338k cycles29.8 per MAC	16.6 ms796k cycles23.5 per MAC	63.2 ms3.03M cycles19.2 per MAC	229 ms11M cycles18.0 per MAC
CC2340R5	M0+, 48 MHz, no FPU	none	TI Arm Clang 4.0.4 prebuilt model library (built for the G3507), test program 5.1.1 plain C, -Os `c-os`	8.37 ms402k cycles35.5 per MAC	20 ms958k cycles28.3 per MAC	83.2 ms3.99M cycles25.3 per MAC	308 ms14.8M cycles24.2 per MAC
CC2340R5	M0+, 48 MHz, no FPU	none	TI Arm Clang 4.0.4 prebuilt model library (built for the G3507), test program 5.1.1 plain C, -Os `c-os-with-ble-basic`	not built	not built	71.9 ms3.45M cycles21.9 per MAC	not built
CC2340R5	M0+, 48 MHz, no FPU	none	TI NNC 2.1.2 with TI Arm Clang 5.1.1 (the G3507 prebuilt model library) TI NNC code, -Os, the MSPM0 G3507 prebuilt model library unchanged `nnc-cpu`	7.96 ms382k cycles33.7 per MAC	20.4 ms980k cycles29.0 per MAC	77.1 ms3.7M cycles23.5 per MAC	268 ms12.9M cycles21.1 per MAC
CC1354P10-1	M33, 48 MHz, FPU	none	TI Arm Clang 5.1.1, model compiled for this chip plain C, -O3 `c-o3`	2.33 ms112k cycles9.9 per MAC	6.22 ms299k cycles8.8 per MAC	25.8 ms1.24M cycles7.9 per MAC	96.4 ms4.63M cycles7.6 per MAC
CC1354P10-1	M33, 48 MHz, FPU	none	TI Arm Clang 5.1.1, model compiled for this chip plain C, -Os `c-os`	3.54 ms170k cycles15.0 per MAC	9.81 ms471k cycles13.9 per MAC	41 ms1.97M cycles12.5 per MAC	155 ms7.45M cycles12.2 per MAC
CC1354P10-1	M33, 48 MHz, FPU	none	TI NNC 2.1.2 C output for the G3507, recompiled with TI Arm Clang 5.1.1 TI NNC code, -O2, NNC's G3507 C recompiled for the Cortex-M33F `nnc-cpu-src-m33`	2.13 ms102k cycles9.0 per MAC	6.05 ms291k cycles8.6 per MAC	24.4 ms1.17M cycles7.4 per MAC	91 ms4.37M cycles7.2 per MAC
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O2, code in flash `c-o2-flash`	1.98 ms237k cycles20.9 per MAC	5.11 ms614k cycles18.1 per MAC	18.2 ms2.19M cycles13.9 per MAC	67.4 ms8.08M cycles13.2 per MAC
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O2, code in RAM `c-o2-ram`	1.72 ms207k cycles18.2 per MAC	4.31 ms518k cycles15.3 per MAC	Not for this chipTest harness adds 10.2 kB of test vectors and a 2 kB stack to the RAM image; weights 17.4 kB fit; about 27 kB without vectors (estimate; not built)	Not for this chipWeights 65.7 kB are more than the 36 kB of RAM; flash build fits
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O4, code in flash `c-o4-flash`	1.82 ms219k cycles19.3 per MAC	4.83 ms580k cycles17.1 per MAC	17.6 ms2.11M cycles13.3 per MAC	65.4 ms7.85M cycles12.9 per MAC
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O4, code in RAM `c-o4-ram`	1.6 ms192k cycles16.9 per MAC	4.11 ms493k cycles14.6 per MAC	Not for this chipTest harness adds 10.2 kB of test vectors and a 2 kB stack to the RAM image; weights 17.4 kB fit; about 27 kB without vectors (estimate; not built)	Not for this chipWeights 65.7 kB are more than the 36 kB of RAM; flash build fits
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O4, speed level 0, code in flash `c-o4s0-flash`	1.86 ms223k cycles19.7 per MAC	4.93 ms592k cycles17.5 per MAC	17.9 ms2.15M cycles13.6 per MAC	66.6 ms8M cycles13.1 per MAC
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O4, speed level 0, code in RAM `c-o4s0-ram`	1.6 ms192k cycles16.9 per MAC	4.12 ms494k cycles14.6 per MAC	Not for this chipTest harness adds 10.2 kB of test vectors and a 2 kB stack to the RAM image; weights 17.4 kB fit; about 27 kB without vectors (estimate; not built)	Not for this chipWeights 65.7 kB are more than the 36 kB of RAM; flash build fits
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O4, speed level 5, code in flash `c-o4s5-flash`	1.8 ms216k cycles19.1 per MAC	4.81 ms577k cycles17.0 per MAC	17.5 ms2.1M cycles13.3 per MAC	65.3 ms7.84M cycles12.8 per MAC
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI C2000 compiler 25.11.1 plain C, -O4, speed level 5, code in RAM `c-o4s5-ram`	1.58 ms189k cycles16.7 per MAC	4.09 ms491k cycles14.5 per MAC	Not for this chipTest harness adds 10.2 kB of test vectors and a 2 kB stack to the RAM image; weights 17.4 kB fit; about 27 kB without vectors (estimate; not built)	Not for this chipWeights 65.7 kB are more than the 36 kB of RAM; flash build fits
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI NNC 2.1.2 with TI C2000 compiler 25.11.1 TI NNC code, -O3, speed level 5 `nnc-cpu`	1.12 ms135k cycles11.9 per MAC	2.6 ms312k cycles9.2 per MAC	9.05 ms1.09M cycles6.9 per MAC	30.8 ms3.69M cycles6.0 per MAC
LAUNCHXL-F2800137	C28x, 120 MHz, FPU	none (the chip has TMU; integer model code does not use it)	TI NNC 2.1.2 with TI C2000 compiler 25.11.1 TI NNC code, -O3, speed level 5, code in RAM `nnc-cpu-ram`	1.11 ms134k cycles11.8 per MAC	2.97 ms357k cycles10.5 per MAC	Not for this chipNNC image is 38.8 kB of flash content plus 9.2 kB of RAM in the flash build; over 36 kB even without the 10.2 kB of test vectors (estimate)	Not for this chipWeights 65.7 kB are more than the 36 kB of RAM; flash build fits
AM13E230	M33, 200 MHz, FPU	none (the chip has TMU and NPU; integer model code does not use it)	plain C, -O3 `c-o3`	0.49 ms98k cycles8.6 per MAC	1.25 ms250k cycles7.4 per MAC	5.05 ms1.01M cycles6.4 per MAC	18.7 ms3.74M cycles6.1 per MAC
AM13E230	M33, 200 MHz, FPU	none (the chip has TMU and NPU; integer model code does not use it)	plain C, -Os `c-os`	0.68 ms136k cycles12.0 per MAC	1.86 ms372k cycles11.0 per MAC	7.61 ms1.52M cycles9.6 per MAC	28.6 ms5.73M cycles9.4 per MAC
AM13E230	M33, 200 MHz, FPU	none (the chip has TMU and NPU; integer model code does not use it)	TI NNC code `nnc-cde`	failed	failed	failed	failed
AM13E230	M33, 200 MHz, FPU	none (the chip has TMU and NPU; integer model code does not use it)	TI NNC code `nnc-cpu`	0.5 ms100k cycles8.8 per MAC	1.38 ms275k cycles8.1 per MAC	5.54 ms1.11M cycles7.0 per MAC	22.9 ms4.58M cycles7.5 per MAC
AM13E230	M33, 200 MHz, FPU	NPU	TI NNC code on the NPU `nnc-npu`	0.11 ms21k cycles1.9 per MAC	0.21 ms41k cycles1.2 per MAC	0.63 ms126k cycles0.8 per MAC	9.53 ms1.91M cycles3.1 per MAC
AM13E230	M33, 200 MHz, FPU	NPU	TI NNC code on the NPU `nnc-npu-container`	0.11 ms21k cycles1.9 per MAC	not built	not built	not built
CC2755P10	M33, 96 MHz, FPU	none	plain C, -O3 `c-o3`	1.01 ms97k cycles8.6 per MAC	2.6 ms250k cycles7.4 per MAC	10.5 ms1.01M cycles6.4 per MAC	39 ms3.75M cycles6.1 per MAC
CC2755P10	M33, 96 MHz, FPU	none	plain C, -Os `c-os`	1.41 ms136k cycles12.0 per MAC	3.86 ms371k cycles11.0 per MAC	15.8 ms1.52M cycles9.6 per MAC	59.6 ms5.73M cycles9.4 per MAC
CC2755P10	M33, 96 MHz, FPU	none	TI NNC code `nnc-cpu-src-m33`	0.95 ms91k cycles8.1 per MAC	2.73 ms262k cycles7.7 per MAC	10.8 ms1.04M cycles6.6 per MAC	40.6 ms3.89M cycles6.4 per MAC
CC35X1	M33, 160 MHz, FPU	none	plain C, -O3 `c-o3`	0.6 ms96k cycles8.5 per MAC	1.54 ms246k cycles7.3 per MAC	6.25 ms1M cycles6.3 per MAC	24.4 ms3.9M cycles6.4 per MAC
CC35X1	M33, 160 MHz, FPU	none	plain C, -Os `c-os`	0.84 ms134k cycles11.9 per MAC	2.32 ms371k cycles11.0 per MAC	9.45 ms1.51M cycles9.6 per MAC	36.3 ms5.81M cycles9.5 per MAC
ESP32-C6-DevKitC-1-N8	RISC-V, 160 MHz, no FPU	none	plain C, -O2, code in flash `c-o2-flash`	1.23 ms197k cycles17.4 per MAC	2.75 ms440k cycles13.0 per MAC	10.1 ms1.61M cycles10.2 per MAC	40.1 ms6.41M cycles10.5 per MAC
ESP32-C6-DevKitC-1-N8	RISC-V, 160 MHz, no FPU	none	plain C, -O3 `c-o3`	1.12 ms179k cycles15.8 per MAC	2.17 ms347k cycles10.2 per MAC	7.14 ms1.14M cycles7.2 per MAC	27.1 ms4.34M cycles7.1 per MAC
ESP32-C6-DevKitC-1-N8	RISC-V, 160 MHz, no FPU	none	plain C, -Os `c-os`	1.62 ms259k cycles22.9 per MAC	3.82 ms611k cycles18.1 per MAC	15.1 ms2.42M cycles15.4 per MAC	57.1 ms9.13M cycles15.0 per MAC
ESP32-C6-DevKitC-1-N8	RISC-V, 160 MHz, no FPU	none	plain C `lpcore-full`	not built	not built	Not for this chipthe network alone fits (2.3 kB left for the stack); see the ESP32-C6 low-power core occupancy experiment	not built
ESP32-C6-DevKitC-1-N8	RISC-V, 160 MHz, no FPU	none	plain C, -Os `lpcore-network-os`	not built	not built	214 ms34.2M cycles216.7 per MAC	not built
LAUNCHXL-F28P65X	C28x, 200 MHz, FPU	none (the chip has TMU; integer model code does not use it)	plain C, -O4, speed level 5, code in flash `c-o4s5-flash`	not built	not built	not built	47.9 ms9.58M cycles15.7 per MAC
LAUNCHXL-F28P65X	C28x, 200 MHz, FPU	none (the chip has TMU; integer model code does not use it)	plain C, -O4, speed level 5, code in RAM `c-o4s5-ram`	0.89 ms179k cycles15.8 per MAC	2.37 ms473k cycles14.0 per MAC	8.38 ms1.68M cycles10.6 per MAC	Not for this chipweights need 0x9823 = 38,947 B; a wider RAM carve-up (RAMGS1-4, currently reserved by unused SDFM/NOINIT placeholder sections) would likely fit it; not tried
FRDM-MCXA153	Cortex-M33, 96 MHz, no FPU	none	plain C, -O3 `armgnu14-c-o3`	1.68 ms161k cycles14.2 per MAC	3.51 ms337k cycles10.0 per MAC	12.6 ms1.21M cycles7.6 per MAC	45.5 ms4.37M cycles7.2 per MAC
FRDM-MCXA153	Cortex-M33, 96 MHz, no FPU	none	plain C, -Os `armgnu14-c-os`	3.07 ms295k cycles26.0 per MAC	10.4 ms996k cycles29.4 per MAC	42.9 ms4.11M cycles26.1 per MAC	163 ms15.6M cycles25.6 per MAC
FRDM-MCXA153	Cortex-M33, 96 MHz, no FPU	none	plain C, -O3 `c-o3`	1.66 ms159k cycles14.1 per MAC	3.6 ms346k cycles10.2 per MAC	12.6 ms1.21M cycles7.7 per MAC	45.8 ms4.4M cycles7.2 per MAC
FRDM-MCXA153	Cortex-M33, 96 MHz, no FPU	none	plain C, -Os `c-os`	3.07 ms295k cycles26.0 per MAC	10.4 ms996k cycles29.4 per MAC	42.9 ms4.11M cycles26.1 per MAC	163 ms15.6M cycles25.6 per MAC
MSPM0 G3519	M0+, 80 MHz, no FPU	none (the chip has MATHACL; integer model code does not use it)	plain C, -O3 `c-o3`	3.91 ms313k cycles27.6 per MAC	9.04 ms723k cycles21.4 per MAC	35.3 ms2.82M cycles17.9 per MAC	129 ms10.4M cycles17.0 per MAC
MSPM0 G3519	M0+, 80 MHz, no FPU	none (the chip has MATHACL; integer model code does not use it)	plain C, -Os `c-os`	4.67 ms374k cycles33.0 per MAC	10.9 ms870k cycles25.7 per MAC	39.9 ms3.19M cycles20.2 per MAC	145 ms11.6M cycles19.0 per MAC
MSPM0 G3519	M0+, 80 MHz, no FPU	none (the chip has MATHACL; integer model code does not use it)	TI NNC code `nnc-cpu`	4.93 ms394k cycles34.8 per MAC	12 ms958k cycles28.3 per MAC	45.6 ms3.65M cycles23.1 per MAC	159 ms12.7M cycles20.9 per MAC
MSPM0 G5187	M0+, 80 MHz, no FPU	none (the chip has NPU; integer model code does not use it)	plain C, -O3 `c-o3`	3.92 ms313k cycles27.7 per MAC	9.05 ms724k cycles21.4 per MAC	35.3 ms2.82M cycles17.9 per MAC	129 ms10.4M cycles17.0 per MAC
MSPM0 G5187	M0+, 80 MHz, no FPU	none (the chip has NPU; integer model code does not use it)	plain C, -Os `c-os`	4.68 ms374k cycles33.0 per MAC	10.9 ms869k cycles25.7 per MAC	39.9 ms3.2M cycles20.2 per MAC	145 ms11.6M cycles19.0 per MAC
MSPM0 G5187	M0+, 80 MHz, no FPU	none (the chip has NPU; integer model code does not use it)	TI NNC code `nnc-cpu`	4.94 ms395k cycles34.9 per MAC	12 ms958k cycles28.3 per MAC	45.6 ms3.65M cycles23.1 per MAC	159 ms12.7M cycles20.9 per MAC
MSPM0 G5187	M0+, 80 MHz, no FPU	none (the chip has NPU; integer model code does not use it)	TI NNC code `nnc-cpu-32mhz`	10.9 ms347k cycles30.7 per MAC	26.6 ms851k cycles25.1 per MAC	101 ms3.23M cycles20.5 per MAC	357 ms11.4M cycles18.7 per MAC
MSPM0 G5187	M0+, 80 MHz, no FPU	NPU	TI NNC code on the NPU `nnc-npu`	1.29 ms103k cycles9.1 per MAC	1.45 ms116k cycles3.4 per MAC	2.12 ms169k cycles1.1 per MAC	69.4 ms5.55M cycles9.1 per MAC
MSPM0 G5187	M0+, 80 MHz, no FPU	NPU	TI NNC code on the NPU `nnc-npu-32mhz`	2.88 ms92k cycles8.1 per MAC	3.23 ms103k cycles3.1 per MAC	4.77 ms153k cycles1.0 per MAC	161 ms5.15M cycles8.4 per MAC
MSPM33 C321A	M33, 160 MHz, FPU	none	plain C, -O3 `c-o3`	0.75 ms120k cycles10.6 per MAC	1.86 ms297k cycles8.8 per MAC	7.38 ms1.18M cycles7.5 per MAC	27.2 ms4.35M cycles7.1 per MAC
MSPM33 C321A	M33, 160 MHz, FPU	none	plain C, -O3 `c-o3-32mhz`	3.04 ms97k cycles8.6 per MAC	7.79 ms249k cycles7.4 per MAC	31.5 ms1.01M cycles6.4 per MAC	117 ms3.73M cycles6.1 per MAC
MSPM33 C321A	M33, 160 MHz, FPU	none	plain C, -Os `c-os`	0.96 ms154k cycles13.6 per MAC	2.62 ms419k cycles12.4 per MAC	10.6 ms1.7M cycles10.8 per MAC	39.7 ms6.34M cycles10.4 per MAC
NUCLEO-U083RC	M0+, 56 MHz, no FPU	none	plain C, -O3 `gcc12-o3`	8.16 ms392k cycles34.6 per MAC	15.3 ms734k cycles21.7 per MAC	51.6 ms2.48M cycles15.7 per MAC	185 ms8.89M cycles14.6 per MAC
NUCLEO-U083RC	M0+, 56 MHz, no FPU	none	plain C, -Os `gcc12-os`	11 ms527k cycles46.5 per MAC	28 ms1.35M cycles39.7 per MAC	110 ms5.28M cycles33.4 per MAC	415 ms19.9M cycles32.6 per MAC
NUCLEO-U083RC	M0+, 56 MHz, no FPU	none	plain C, -O3 `stgcc14-o3`	8.05 ms386k cycles34.1 per MAC	15.3 ms732k cycles21.6 per MAC	52 ms2.49M cycles15.8 per MAC	186 ms8.91M cycles14.6 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -O3 `c-o3-m33`	0.75 ms112k cycles9.9 per MAC	1.89 ms283k cycles8.4 per MAC	6.82 ms1.02M cycles6.5 per MAC	27 ms4.06M cycles6.6 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -O3 `c-o3-m33-gcc12`	0.76 ms114k cycles10.1 per MAC	1.93 ms290k cycles8.6 per MAC	7 ms1.05M cycles6.7 per MAC	27.6 ms4.14M cycles6.8 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -O3, code in RAM `c-o3-ram-m33`	0.76 ms114k cycles10.1 per MAC	1.9 ms285k cycles8.4 per MAC	6.99 ms1.05M cycles6.6 per MAC	25.9 ms3.88M cycles6.4 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -O3, code in RAM `c-o3-ram-riscv`	0.99 ms149k cycles13.2 per MAC	2.09 ms313k cycles9.3 per MAC	7.58 ms1.14M cycles7.2 per MAC	27.3 ms4.09M cycles6.7 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -O3 `c-o3-riscv`	0.99 ms148k cycles13.1 per MAC	2.1 ms314k cycles9.3 per MAC	7.5 ms1.13M cycles7.1 per MAC	29 ms4.35M cycles7.1 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -Os `c-os-m33`	1.38 ms207k cycles18.2 per MAC	4.36 ms654k cycles19.3 per MAC	18 ms2.7M cycles17.1 per MAC	71.6 ms10.7M cycles17.6 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -Os `c-os-m33-gcc12`	1.38 ms207k cycles18.3 per MAC	4.35 ms653k cycles19.3 per MAC	18 ms2.7M cycles17.1 per MAC	71.6 ms10.7M cycles17.6 per MAC
Raspberry Pi Pico 2 H	Cortex-M33, 150 MHz, no FPU	none	plain C, -Os `c-os-riscv`	1.48 ms222k cycles19.6 per MAC	3.79 ms568k cycles16.8 per MAC	15.2 ms2.28M cycles14.5 per MAC	61.9 ms9.29M cycles15.2 per MAC
SK-TDA4VM	2x Cortex-A72 + C7x/MMA + 2x C66x + 6x R5F, 2000 MHz, no FPU	none	plain C, -O3 `c-gcc-o3-a72`	0.02 ms35k cycles3.1 per MAC	0.04 ms89k cycles2.6 per MAC	0.19 ms386k cycles2.4 per MAC	0.69 ms1.37M cycles2.2 per MAC

The MSPM0 C1104 cells and the MSPM0 L1306 33k-parameter cells: the model's own buffers are more than the chip's RAM. The LAUNCHXL-F2800137 "code in RAM" cells for the two larger models: the test program puts the weights or the test vectors in RAM, and the same models run from flash.

Model sizes, from mspm0g3507/mcu-bench/edgeai/uci-room-occupancy/<model>/layers.json:

636 parameters: 636 parameters, 11k MACs, 1.1 kB of buffers in RAM
1.7k parameters: 1.7k parameters, 34k MACs, 1.1 kB of buffers in RAM
8.5k parameters: 8.5k parameters, 158k MACs, 2.1 kB of buffers in RAM
33k parameters: 33k parameters, 611k MACs, 4.1 kB of buffers in RAM

Cycles are derived: milliseconds times the clock. Each time is the fastest of the 20 test vectors; each board ran with the CPU never sleeping. The MSPM0 G3507 and MSPM0 L1306 rows are single runs; the others are 3 to 5 runs. Sources: cc35x1/occ/occ_run.c.

What moves the number

Clock: the same chip at two clocks

Clock	Cycles	Time
32 MHz	2.64M	82.5 ms
80 MHz	2.75M	34.4 ms

MSPM0 G3507, BitNetMCU (an open-source tiny handwritten-digit network) 64-channel digit model, same build. 2.5 times the clock made it 2.4 times faster, not 2.5. The cycle count rose 4%, probably from flash wait states at the higher clock (suspected, not isolated). The occupancy models show the same build taking more cycles at the higher clock: MSPM0 G5187: 8 to 14% more at 80 MHz than at 32 MHz; MSPM33 C321A: 17 to 23% more at 160 MHz than at 32 MHz. Source: ports/bitnetmcu/README.md.

Where the code runs counts too: on the LAUNCHXL-F2800137 the smallest occupancy model takes 1.58 ms from RAM and 1.8 ms from flash (14% more), same compiler and flags. Flash wait states are the suspected cause.

M0+ chip against M33 chip, both at 48 MHz

Model	Cortex-M0+	Cortex-M33	M33 faster by
636 parameters	7.03 ms	2.33 ms	3.0x
1.7k parameters	16.6 ms	6.22 ms	2.7x
8.5k parameters	63.2 ms	25.8 ms	2.4x
33k parameters	229 ms	96.4 ms	2.4x

CC2340R5 (M0+) against CC1354P10-1 (M33), both at 48 MHz, both plain C at -O3 with code in flash: only the clock and the -O3 setting match. Three things differ. The core differs. The flash system differs: the CC2340R5 reads flash with 2 wait states and a cache, per cc2340r5/bench/RESULTS.md. The model's compiler differs: TI Arm Clang 4.0.4 prebuilt model library on the M0+, 5.1.1 on the M33. So the ratio is for each chip and its build together. The models use no floating point, so the M33's FPU plays no part.

Per MAC on the 33k-parameter model: 18.0 cycles on the M0+, 7.6 on the M33, 12.8 on the C28x (LAUNCHXL-F2800137, plain C, -O4, speed level 5, code in flash, at 120 MHz with a different compiler).

Floating point against integer

Board	Core	q15 fixed point, cycles	32-bit float, cycles	Float costs
CC2340R5	M0+, no FPU	81k	878k	10.9x
CC1354P10-1	M33, FPU	16k	23k	1.4x

A 256-point FFT (fast Fourier transform, which turns samples into frequencies), the same job in 16-bit fixed point (q15, whole-number math in 16 bits) and in 32-bit float, both on the same board. Without an FPU, float runs in software. Each ratio compares two builds on one board. The boards also differ in core and DSP library, so the FPU is probably most of the gap between the ratios, but it was not isolated. Source: cc1354p10/bench/results/fft-O3.txt.

The same holds for control math: one motor-control step on the MSPM0 L1306 takes 13k cycles in float and 1.7k in TI's IQmath fixed point, 7.3 times fewer. Source: mspm0l1306/bench/ctrl/README.md.

All four occupancy models are 8-bit integer (int8), which is why they run at all on a Cortex-M0+ without an FPU. A float model on a chip with no FPU would pay a cost like the one above.

A code generator against plain C, and the NPU chips

Board	Core	TI NNC code	Plain C at the same flags	Fastest plain C
LAUNCHXL-F2800137	C28x, FPU	30.8 ms -O3, speed level 5	no matching build	65.3 ms: NNC 2.12x faster plain C, -O4, speed level 5, code in flash
CC1354P10-1	M33, FPU	91 ms -O2, NNC's G3507 C recompiled for the Cortex-M33F	no matching build	96.4 ms: NNC 1.06x faster plain C, -O3
MSPM0 G3507	M0+, no FPU	159 ms -Os	199 ms: NNC 1.25x faster (the plain C -Os figure is a single run under recheck)	129 ms: NNC 1.23x slower plain C, -O3
CC2340R5	M0+, no FPU	268 ms -Os, the LP-MSPM0G3507 prebuilt model library unchanged	308 ms: NNC 1.15x faster	229 ms: NNC 1.17x slower plain C, -O3

The 33k-parameter model. TI's Neural Network Compiler (NNC) turns the model into C for the CPU. On the Cortex-M0+ boards NNC's code was built at -Os, TI's setting for the M0. It beats plain C at -Os on this model, but plain C at -O3 is faster still. On the C28x it about halves the time against the closest plain C build. None of these CPU rows uses an NPU.

The MSPM0 G5187 and AM13E230 have an NPU; their NPU rows are measured (build names with npu).

LP-MSPM0G5187, NPU at 80 MHz: 636 parameters: 1.29 ms, 9.12 cycles per MAC; 1.7k parameters: 1.45 ms, 3.43 cycles per MAC; 8.5k parameters: 2.12 ms, 1.07 cycles per MAC; 33k parameters: 69.4 ms, 9.09 cycles per MAC. TI NNC has already compiled all four occupancy models for this chip's NPU (for the 33k-parameter model it kept one convolution on the CPU).
LP-AM13E230, NPU at 200 MHz: 636 parameters: 0.11 ms, 1.88 cycles per MAC; 1.7k parameters: 0.21 ms, 1.21 cycles per MAC; 8.5k parameters: 0.63 ms, 0.8 cycles per MAC; 33k parameters: 9.53 ms, 3.12 cycles per MAC. Cortex-M33 at 200 MHz with an NPU and a TMU. TI's compiler built the four models for the NPU and for the CPU, both measured here; TI's own motor fault example is not run, because the SDK ships them as prebuilt libraries with no CPU twin.

Results FAQ

Why do none of the four occupancy models fit the MSPM0 C1104?: The chip has 1 kB of RAM and the smallest model's buffers need 1.2 kB: the model's 1.1 kB plus 48 B for the test program. The build stops with a linker error. This is a link-only result from before the board arrived, for these models as built. The largest model's weights alone (33.6 kB) are also over its 16 kB of flash. Smaller models, such as the 1k digit model from BitNetMCU (an open-source tiny digit-recognising network), do link. Source: mspm0c1104/bench/prebuild-2026-10-08.md.
Why does the smallest model cost more cycles per MAC than the biggest?: A fixed cost per inference is suspected, such as quantizing the input and setting up each layer. It weighs more on 11k MACs than on 611k, but it was not isolated. Use the large-model figure for a large model; the explorer on the page shows the spread.
Is TI NNC faster than plain C?: On the C28x, yes: about twice as fast. On the Cortex-M0+ boards it depends on the model and the flags. NNC's code was built at -Os. On the MSPM0 G3507 it was 6 to 14% slower than plain C at -Os on the three smaller models and faster on the largest. Plain C at -O3 beat it on every model. The G3507's plain C -Os figure for the largest model is 26.1 cycles per MAC, against 20.2 for the next size down. That runs against every other board's trend and is a single run, so it needs a rerun. No NNC build at -O3 was made.
Why does the 33k-parameter model not fit the MSPM0 L1306?: Its activation buffers alone need 4.1 kB and the chip has 4 kB of RAM, so the build stops with a linker error. The three smaller models run on it.
Why do some LAUNCHXL-F2800137 RAM builds say No: RAM when the same model runs?: Running from RAM avoids flash wait states, so each model was also built with its code and data in RAM. For plain C, the 33k-parameter model's weights are 65.7 kB against 36 kB of RAM. The 8.5k-parameter build also carries 10.2 kB of test vectors. The linker said `program will not fit into available memory` (c2000-launchpad/bench/edgeai/build-occ_cnn_8k-4-RAM/build.log). The NNC 8.5k-parameter RAM build is over the RAM even without the test vectors. That rests on an estimate of 38.8 kB of flash content plus 9.2 kB of RAM, not built to the end. Run them from flash, as the flash rows do.
How much faster is the Cortex-M33 chip than the Cortex-M0+ chip at 48 MHz?: 2.4 to 3.0 times, by model size, in the measured rows: plain C at -O3 on the CC1354P10-1 (M33) against the CC2340R5 (M0+). The two differ in core, flash system and compiler build, so the ratio is not the core alone. Flash wait states are the suspected part of the gap. The same build was not run on both.
What does floating point cost on a chip with no FPU?: A 256-point FFT took 10.9 times the cycles in 32-bit float than in q15 on the CC2340R5 (no FPU) and 1.4 times on the CC1354P10-1 (FPU). The occupancy models are int8, so they avoid that cost.
Why does the measured 176 ms for TI's motor bearing fault example differ from TI's published 229.01 ms?: TI's example ran as shipped on the MSPM0 G3507 at 80 MHz, one run. One run, reason not found. Compiler version, flags or clock setup are possible, but this was not checked.
Why is the MSPM0 G3507 waveform classifier (hello_world_ai) timed at 32 MHz?: That row ran at the example's own 32 MHz setting. The other MSPM0 G3507 rows ran at 80 MHz, so the times are not comparable. The data records the clock but not why the example uses 32 MHz.
What does the linker message look like?: On the LAUNCHXL-F2800137 the linker printed program will not fit into available memory (c2000-launchpad/bench/edgeai/build-occ_cnn_8k-4-RAM/build.log). For the Arm chips the table records the sizes, not the message.
Where are the NPU numbers?: In the section on the NPU against the CPU, higher on this page, and as NPU dots in the explorer. A board with no row has no estimate.

AI that runs on the chip. How the numbers are made: Method. For AI tools that write code, see Build with AI. Working demos: handwritten digits, a small AI model.